As channel lengths of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) are shortened unceasingly, a series of effects, which may have been ignored in MOSFET long channel models, now become increasingly remarkable and even become major factors that unfavorably affect device performance, and such phenomena are generally referred to as short-channel effects. Electrical properties of devices are deteriorated because of short-channel effects; for example, short-channel effects may cause decrease of gate threshold voltage, increase of power consumption and reduction of Signal-to-Noise Ratio (SNR).
In order to alleviate short-channel effects, Super-Steep Retrograde Well (SSRW) is now introduced into semiconductor FET devices. SSRW has a low-high-low (or low-high) channel doping profile, that is, surface regions of the channel have a low doping concentration, while highly doped regions are formed beneath the channel surfaces through ion implantation or other methods as appropriate, so as to reduce width of depletion regions at source/drain regions and, meanwhile, to suppress short-channel effects like increase of leakage arising from source/drain punch through and increase of threshold voltage. The U.S. patent numbered U.S. Pat. No. 7,002,214 has already disclosed super-steep retrograde well (SSRW) FET devices on ultra-thin body silicion on insulator (UTBSOI). As shown in FIG. 1, heavily doped SOI regions 33L/33R are formed on SOI through ion implantation, then ultra-thin intrinsic epitaxial regions 48L/48R are grown, so as to form super-steep retrograde doped channel profile and further to form an FET device. However, it is difficult to control doping profile through ion implantation; besides, it is also quite difficult to grow an epitaxial layer of high quality at a heavily doped region. The traditional SiGe PMOS stressed silicon technology also encounters up its bottleneck in development and thus is unlikely to provide stronger stress for channels anymore. Furthermore, bottleneck in development will soon be seen in respect to thickness of gate oxide dielectric, since the speed of thinning gate oxide has already fallen behind to the pace of reducing width of gates, consequently, gate dielectric leakage increases gradually; because critical dimension is downscaled constantly, thus it will easily give rise to continuous increase of resistance at source/drain regions and increase of power consumption of devices accordingly.
Nowadays, the dominant trend in the industry focuses on improving technologies of traditional planar devices, endeavoring to reduce thickness of channel regions and removing neutral regions at the bottom of depletion regions within the channel, such that the depletion regions in the channel are able to fill the channel regions completely—this is the so-called Fully Depleted (FD) device, whereas traditional planar devices are Partially Depleted (PD) devices.
However, silicon layers at channel regions must be very thin in order to manufacture FD devices. It is hard to manufacture a desired structure or it costs considerably high according to the traditional manufacturing process, especially, according to the traditional manufacturing process based on bulk silicon; it is still very hard to keep the thickness of silicon layers within the channel at a very thin level even in novel SOI (Silicon-on-Insulator) process. Therefore, on the basis of comprehensive thoughts of how to realize FD devices, the focus of research and development is shifted to three-dimensional device structures, i.e., to FD double-gate or tri-gate technologies.
Three-dimensional device structures (also referred to as vertical devices in some other articles) indicate devices whose cross-sectional planes of source/drain regions and cross-sectional planes of gates are not located on the same plane, which in essence are FinFET (Fin Field-Effect Transistor) structures.
In three-dimensional device structures, channel regions are separated from bulk silicon or SOI instead of being embraced therein, which thus makes it possible to manufacture very thin FD channels by means of etching or the like.
At present, the three-dimensional semiconductor device that has been proposed in the prior art is as shown in FIG. 2, which comprises a semiconductor base 020 located on an insulating layer 010, source and drain regions 030 in contact with first sidewalls 022 of the semiconductor base 020 opposite to each other, and gates 040 located on second sidewalls 024 adjacent to the first sidewalls 022 of the semiconductor base 020 (a gate dielectric layer and a work function metal layer sandwiched between the gate 040 and the semiconductor base 020 are not shown). Wherein, in order to reduce resistance at source and drain regions, the peripheries of the source and drain regions 030 may be extended; namely, the width of the source and drain regions 030 (in the XX′ direction) is greater than the thickness of the semiconductor base 020. Three-dimensional semiconductor structures are expected to be applied in 22 nm technical node or below; however, along with further downscaling of device size, short-channel effects in three-dimensional devices will also become major factors that affect performance of the devices.